Storage circuits



` Feb. s, 1966 2 Sheets-Sheet 1 Filed Feb.

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Arran/EY INV EN TOR.

LST

Feb. 8, 1966 s. B. DINMAN v 3,234,401

STORAGE CIRCUITS Y Filed Feb. 5, 1962 2 Sheets-Sheet 2 www.; /fVP//rs f I i L Y MAJ MAJ. MAJ

10 JNVENToR.

.tit can be implemented with only two transistors.

tice

United States Patent puits. are -us'eful .in. digital computers :although they are z' notrestricted to this use.

l.Agfle'xible logicelernent. is.one which receives one or jrnoreinformation signalinputs indicative of binary bits rand oneorinore control signal inputs indicative of binary bitsrandwhich producesone. or more output signals indicative of. binary bits.v l The logic. function performed by l.jthecincuit `is a function of the value or values ofl the ,.;controlsignals., It is inthissense that theelement is fiiexiblef Vthat is, capable Iof` operating in different ways. An objectrof thisinvention isto provide new and improved- .storage circuits, employing flexible logic elements. l. Anothenobjectfof this invention is to provide new and ,useful yo.nigurations of minority gateyiiexible logic ele- 5. ments.

AAnother,objectof the present invention is to provide an .zimproved '.strobed `inputip,ilop. y A strobed input flipv4flop.is.one,Which'receives a yset signal, a reset jsignal, and a third signal-known as a strobe signal. In the absence f;offthestrobesignal, .the set and reset Lsignals have no effect '..on the;.informationgstored inthe ,ip-nop. Theiiip-iiop can be set or reset;only whenythe` strobe signal is applied '.concurrently with the setortzreset signal.

.Acircuitzmodule according to the present invention Vfconiprises';agpairlof minority` gates, eachreceivingr the same 1 control signal. and the Vtwosreceiving complementary :information `signals. The output ofeach ,gate lserves as ..an;inputtoxthe.otherytgatewand is weighted more heavily than eitherthegcontrolor; information signal input to said .other,.`gate. .-fI`hismoduleis astrobed inputfiiip-op and Alternatively, other thresholdflogic ,elements such .as cores, tubes or tunnel diodes .may beyernployed `as t the .minority n gates. 1 Numbers of ,Suchmodules maybe interconnected invarious waysto provide more complexcircuits such .t-,asregis'tern counters and the-like.

sistorized. minority gate iiipfiiop such; as-shown inrFIG. 2

but employingbthe"circuitof FIG. 4;

l FIG. 6.isarschematiodiagramtof a minorityigatek maggjnetic :core circuit;

QF'IG.y 7: is a1blockdiagram of aamajoritylogic` gate; PIG.` 8 is: ablockcirouit ,diagram of a majority .gate 1. strobeduinputiiilip-ilop according; to` the present invention;

' FIGtf9-4 is `a :block circuit diagram .of the circuit of'FIG. 2"'.inwhichtle gate of FIG. 'la is employed.

Arnu'mberpoffthexblocks shown in the iigures represent ffknownvcircuits. Thecircuits ofthe. blocks are actuated gates.

. Ratented 8,Vv 514966 `by signals appliedjtolthe blocks. -.When a'fsignal is at one'level,.lit representsfthefbinary digit ff'pneand when it is at anotherl level, it represents ,fthe ,binary-'digit .zero`.

For the sake of the discussion which follows, itmay be assumed that ..rhghY leveLfsignal represen'ts; 'thejlbinary digit one and a`low level signal, thebinarydigitmzero. Also, to simplify/.the discussion, rather than speaking of an electrical-signal .beingfappliedlo a block or logic stage, it is sometimes stated `that affone or a zero is applied to theqblock orlogiestage.

t Throughout theiig'ure'sfcapitalletters are used to represent signals indicative of binary'digits.y For example, S may "representt-hebinaryf digit -zero-or`1the'v binary digit one S represents'the complement of S. *In a numberfof cases, letters areiemployedin Boolean'equations as a lconvenient meansfor describing" the circuit i operation. f

Equation 2 is the Booleangequationjfor a,. .norr.gy gate.

Theequationstates that lthe.,gene:produces a fonertoutput when and only "Whenfall inputs. tothe gatetareffzero.

`When P in Equation l` is equal to "0 Equation 3 isthe equationfor a threerinputlminorityggate.

value .of the output is equalto thatoithe minority of the inputs.

ylf twol of the inputs of the;circuit-ofEguation 3 .are connectedltogether, thenD,the ontputrisutheI complement of the valuepof` thesetwoninputs, regardless' .of .the value ofthe third input. For example,.if `and..B are connected togetherand,representthe.` binary/...blt .fone, then D equals zero regardlessfofr-whether Cf. is ffone or .z,ero. Similarly, if .A'and Bare..connectedtogether and -represent the binary. lbit `zerofi 'then D lis .one regardless of thevalue ofC. t

Since oneoftheA inputs to. the gate of EIG. la isA always a |one, ,this gategnay .begj'shown` as a"1 outfof 4 minority gatehsuac'hasillnstrateddn FIG. .1b. .The Boolean equation for this gate is egractly..the.sameasfthe equationtof the gate of FIG- 1a. I'fthr'ees offtheinputs D is -zero,. and so von. ...In thedig-ure-s .which.follow,

the gate oflFIGS. la and :lbv are representedschematically by the symbol showncin FIG. lc.

A strobed input flip-flop according tothe .present `invention ispshown in FIG. 2. --It includes `twotminority gates `1t? andlZ. The strobe input? is applied to `both The set input Sis appliedl to .terminal Mot -minority gate 10 and .the reset inputA R is `applied to terminal 16 of minority gate 712. The Xl or v0 output of the flip-flop is the output of gate.v 10 and. servesas two inputs to gate 12. Similarly, the Y or 1 output of the Hip-flop is the output of gate 12 and serves as two inputs to minority gate 10.

In the operation -of the ip-flop of FIG. 2, the following values are possible for S and R: S=l, R={); 8:0,

,R=1; S=0, R=0. As in other flip-flops, S cannot be one at the same time as R is one as this would lead to an indeterminate condition.

The Boolean equations for the ip-ops are:

X=fP+s+sP X=(I)P+(I7S+I)F The operation of the dip-flops may most easily be understood by assuming diiferent values for P, the strobe input. When P=0, then X= and, Y=. This shows that in the absence'of a strobe Signal, the output of the Vflip-dop remains the same regardless of the values of S and R. In other words,` if P is zero and a one is applied to the set or reset terminal, the one has `no effect on the information stored in the flip-dop.

When P is made one, then Y X=rs (6) and Y=X R (7) If Y is assumed to be zero under these conditions, then if S is zero, X is one, and if S is made one, then X becomes zero and Y becomes one. If, under the same conditions, X is assumed to be zero and R is zero, Y is one; but if R is made one, Y becomes zero and X becomes one It is therefore clear that in the presence of a strobe pulse (P=1), a one applied to the set terminal 14 produces a Y=1, X= output and a one applied to the reset terminal 16 produces a Y=0, X=1 output. ,Y

An important advantage of the circuitY of FIG. 2 is that itcan be implemented with only two transistors or Similar elements. (A schematic drawing appears later.)

In a Iprevious circuit shown in FIG. 3, our'transistors v were required to perform the same function.

values of S and R. YWhen P is made one (P is made 1 Y the one of FIG. 3` is lthat the former is of much higher speed. For example, in order to set or reset the circuit of FIG. i2, the set or reset signal needs to pass through only one transistor to produce an output. In the circuit of FIG. 3, the set or reset signal must pass through two transistors.

One way in which the circuit of FIG. 2 may be imple- 4rnented is with the transistorized minority gate circuit shown in FIG. 4. The latter includes four input terminals legended A, B, C and P to correspond to FIGS. la and lb'.v These are connected through resistors 30 to the base 32 of transistor 34. The biasing means for the tran- VR is applied. The common ground symbol is used toV indicate the return current paths for the various sources.-

The emitter 44 of the transistor is connected to ground and the .Collelol 46 is connected through resistor 48 to a The base is also connected through Y negative voltage source VO Diode'50 connected to the collector clamps the latter to clamping voltage level VCL, when the diode conducts.

In the explanation of the circuit of FIG. 4 'which follows, it is assumed that ground represents the binary bit one and 6.5 volts represents the binary bit zero The quiescent biasing means for the base 32 of the transistor corresponds to the l control signal input of FIG. la. This biasing means maintains the base of the transistor at a value below that which will cause the transistor to conduct. Diode 40, however, does conduct. When transistor 34 does not conduct, its collec-tor is maintained at a voltage of approximately 6.5 volts corresponding to binary zero by the conducting diode 50.

If the inputs A, B, C and P are all at ground, that is, all represents the binary bit one, transistor 34 remains cutoi and the output D represents the binary bit zero If one of the inputs such as A receives a 6.5 vvolt signal representing the binary bit zero, the diode 4t) conducts less heavily, however, transistor 34 remains cut-olf. Therefore, the output D still represents the binary bit zerof When two inputs such as A and B are both placed at 6.5 volts, diode 40 still conductsand the transistor 34 remains cut'ol. Therefore, the output D is still zero However, when three or m-ore of the inputs receive a 6.5 volt signal representing the binary bit zero, there is noy longer a forward voltage drop across diode 4h and it cuts off. The base voltage now goes negative to a value determined by a value of the voltage divider 38 and the ones of the parallel resist-ors 30 which conduct current. The negative voltage appearing on the base is sufficient to render the transistor 34 conductive causing Athe diode 50 to cut olf and the collector 46 to go to ground. The output D therefore represents the binary bit one When all four inputs A, B, CandP represent the binary bit zer-o, the transistor 34 conducts somewhat more heavily, however, the collector remains at ground and still represents the binary bit one The lcircuit of FIG. 5 shows how the transistorized minority gate of FIG. 4 may be employed in the minority gate hip-ilop. The blocks 52a and 52b of FIG. 5 correspond to the circuits within dashed block 52 of FIG. 4.

The resistors 30a and 30b of FIG. 5 correspond to the resistors 30 of FIG. 4. The interconnection and operation of the flip-flops is self-evident from the explanation of FIGS. 4 and 2. The input leads Vare labeled similarly to the ones of FIG.l 2 to enable the reader easily to see the correspondence between figures. The circuitof FIG. 6 represents asimple magnetic cor circuit connected to 4act as a minority gate. The core circuit may include a sense amplier (not shown) connected Y to the output terminal D and means for enabling the F stable state representing the binary bit zero.

same during the'interval the core changes its state. The amplier is conventional, its purpose being to sense the bit stored in the core and to produce an outputsignal indicative ,of the bit which may be stored as a voltage level in a transistor ip-iiop or the like. It may be as- "surned that the initial state of the core 54 vrepresents storage of the binary bit one and Vthat the inputs applied all represent the binary bit zero. The circuit is so arranged that at least three inputs indicative of the binary bit one are required to switch the core to its other A pair of these can be interconnect-ed in a suitable manner to function as a strobed, minority Ygate flip-lop The circuit of the present invention has been stated to be applicable to minority gates. They may employ majority gates instead. A majority gate may'have anodd ynumber of inputs and has an output whichY is equal in value to that of the majority of inputs. One such gate is shown schematically in FIG. 7. As is understood by those skilled in the art, majority logic is the negation of 'minority logic. Therefore, if inputs are applied to the majority gate which are opposite to the Vinputs used for the minority gate, the majority gate is the full equivalent of the majority gate. Such inputs are shown in FIG. 7. The equations for the gate of FIG. 7 are identical with Equa tion l, 2, 3 for the minority gate discussed above.

The connection of two majority gates as a strobed input ip-fiop is shown in FIG. 8. This llip-flop is the equivalent of the flip-Hop shown in FIG. 2. Note, however, that the inputs are opposite to, that is, the negation of the inputs of FIG. 2. Each majority element is similar to the one of FIG. 7, however, the continuously applied zero input is not shown. The circuit of FIG. 8 may be implemented with transistors similarly to the circuit of FIG. 2.

The claims which follow all call for minority gates.

It is to be understood that the term minority gate is intended to cover the equivalent majority gate circuits such as shown in FIG. 8.

What is claimed is: 1. ln combination, la pair of minority gates; means coupled to the two gates for applying the same control signals to the two gates; means coupled to the two gates for applying an information signal to one gate and a complementary information signal to the other gate; and means for applying the output of each gate as an input to the other gate which is weighted substantially differently than the control and information signal inputs to the other gate. 2. In combination, a pair of minority gates; f me-ans coupled to the two gates for applying the same control signals to the two gates; means coupled to one of the gates for applying an information signal of the same weight as the control signal to said gate; means coupled to the other gate for applying an nformation signal which is complement-ary to the iirst information signal and of the same Weight as the control signal to the other gate; and means for applying the output of each gate as an input to the other gate which is Weighted substantially more heavily than the control and information signal inputs to the other gate. 3. In combination, a pair of minority gates;

means coupled to the two gates for applying the same control signals to the two gates;

means coupled to one of the gates for applying an information signal of the same Weight as the control signal to said gate;

means coupled to the other gate f-or applying an information signal which is complementary to the rst information signal and of the same weight as the control signal to the other gate; and

means for applying the output of each gate as an input to the other gate which is weighted substantially twice as heavily as the control and information signal inputs to the other gate.

4. In combination,

a pair of live-input minority elements;

means for applying a lirst control signal indicative of the binary digit l to the rst input to each gate and a second control signal which can assume a value indicative of the binary digit "1 or "0 to the second input to each gate;

means for applying as the third input to each gate complementary information signals, respectively; and means for applying the output of each element as the fourth and fifth inputs to the other element.

5. In combination,

means providing a control stimulus having one of two values;

a pair of logic elements to which said control stimulus is applied which in response to one value of said control stimulus operate as nor elements and in response to the other value of said control stimulus operate as minority elements;

means for cross-connecting the output of each element,

Weighted substantially more heavily than the control stimulus, to the input of the other element; and

means for applying information inputs to said elements.

References Cited by the Examiner UNITED STATES PATENTS 2,999,637 9/ 1961 Curry 23S- 175 3,088,668 5/1963 Harel 307-885 3,107,306 10/1963 Dobbie 307-885 3,113,206 11/1963 Harel 235--176 IRVING L. SRAGOW, Primary Examiner. 

1. IN COMBINATION, A PAIR OF MINORITY GATES; MEANS COUPLED TO THE TWO GATES FOR APPLYING THE SAME CONTROL SIGNALS TO THE TWO GATES; MEANS COUPLED TO THE TWO GATES FOR APPLYING AN INFORMATION SIGNAL TO ONE GATE AND A COMPLEMENTARY INFORMATION SIGNAL TO THE OTHER GATE; AND MEANS FOR APPLYING THE OUTPUT OF EACH GATE AS AN INPUT TO THE OTHER GATE WHICH IS WEIGHTED SUBSTANTIALLY DIFFERENTLY THAN THE CONTROL AND INFORMATION SIGNAL INPUTS TO THE OTHER GATE. 